Gate array macro cell

ABSTRACT

A gate array macro cell combines the functions of a single SRAM bit and two ROM bits in order to fully utilize all of the transistors in two CMOS gate array core cells, therein increasing the efficiency of implementing memory on a gate array. The SRAM is a six transistor memory cell and each ROM bit is provided by a P-channel field effect transistor. The SRAM and each ROM bit may be accessed separately since each bit is provided with its own word and bit lines.

FIELD OF THE INVENTION

This invention relates in general to gate arrays and, more particularly,to a gate array macro cell having improved efficiency wherein a singleSRAM bit is combined with two ROM bits to utilize all prediffusedtransistors in the core cell.

BACKGROUND OF THE INVENTION

To satisfy the demand for large scale digital integrated circuits, thesemiconductor industry has developed three basic approaches. Theseinclude standard, off the shelf circuits, custom circuits, andsemicustom circuits. The standard, off the shelf circuit provides thelowest cost option due to the quantities manufactured, but are limitedin providing the flexibility for the circuit desired. The custom circuitrequires a long design cycle and is cost limiting unless the number ofcircuits desired is large. The semicustom circuit includes both standardcell and gate array chips. The semicustom approach provides a shorterdesign cycle time and lower engineering costs, but also has lowerperformance and transistor densities than the custom designs.

The gate array involves a standard array of a large number of predefinedtransistors diffused into a chip. The building block of the array is thecore cell which typically includes two, four, or eight transistorsarranged for maximum connectivity for forming many circuit functions.These core cells are then arranged in a plurality of rows and columns toform the array. In addition to the array, the periphery of the gatearray is defined by input/output cells wherein the transistors are alsopredefined. A macro cell library is also designed which defines themetallization patterns necessary to interconnect the transistors withinone or more core cells to form basic logic functions such as inverters,Nand and Nor gates, flip-flops, input and output cells, etc. A customerdefines a design for the gate array by using macros from the macro celllibrary and specifying their interconnection to form the desired systemfunctions.

The advantage of the gate array approach is in its low cost and shortcycle time. And with product lifetimes decreasing there is tremendouspressure to reduce design and manufacturing times. The cost savings comefrom reduced engineering requirements and fewer custom mask setsrequired. This is because many wafers are processed up to the transistorlevel and then stored until they are needed for a customers design. Inthis way all customers share the cost of the masks required to processup to the transistor level in which case the cost becomes negligible.And since the transistors are predefined, it is not necessary to customdesign and layout each of thousands of transistors. Time is saved bothin design time and manufacturing since less engineering is required andthe majority of the processing has been completed before a design isundertaken.

There are several disadvantages associated with the gate array designapproach including lower transistor density due to inefficienttransistor layout and many unused transistors which results in a largerchip, and lower performance. The cost per chip is higher, but for lowvolumes this is offset by the much lower engineering costs. As gatearrays evolve into larger die with more transistors it becomes possibleto realize more complex systems on chip. This increases the need formore specialized macros with greater efficiency (i.e. less unusedtransistors). A specific problem is that of supplying memory efficientlyon the gate array.

In providing Static Random Access Memory (SRAM) two options areavailable: providing a dedicated memory block on the chip, thereinproviding improved density and performance at a cost of flexibility; orproviding a SRAM cell in the macro cell library which is flexible butinefficient (i.e., in a four transistor core cell, two core cells arerequired to implement a six transistor SRAM and thus wastes 2transistors or 25 percent of the area). The same options and problemsexist for providing Read Only Memory (ROM) on the gate array except thatthe problem is exacerbated by the fact that only P or N-channeltransistors could be used in the ROM array, thus wasting 50 percent ofthe transistors in the core cells implementing the ROM array.

Thus, what is needed is a gate array macro cell having improvedefficiency wherein a single SRAM bit is combined with two ROM bits toutilize all prediffused transistors in the core cell.

SUMMARY OF THE INVENTION

Accordingly, it is an object of the present invention to provide animproved gate array macro cell.

It is a further object of the present invention to provide a gate arraymacro cell having combined SRAM and ROM memory functions.

Still it is another object of the present invention to provide a gatearray macro cell having combined SRAM and ROM memory functions whereinthe SRAM and ROM memory bits may be accessed independently.

It is yet another object of the present invention to provide a gatearray macro cell having combined SRAM and ROM memory functions whereineach transistor of the macro cell is utilized.

It is yet still a further object of the present invention to provide animproved method of implementing SRAM and ROM on a gate array.

In carrying out the above and other objects of the invention in oneform, there is provided a macro cell having a SRAM storage cell incombination with first and second ROM storage cells wherein in each ofthe SRAM and first and second ROM storage cells has its own word linesand bit lines. The macro cells comprises a first gate array core cellhaving first and second P-channel and first and second N-channel fieldeffect transistors; a second gate array core cell having first andsecond P-channel and first and second N-channel field effecttransistors; a first plurality of metallization patterns for couplingthe first and second P-type transistors of the first core cell, and thefirst and second N-type transistors of the first and second core cellsfor providing the static RAM storage cell; and a second plurality ofmetallization patterns for coupling the first and second P-typetransistors of the second core cell for providing the first and secondROM storage cells.

The above and other objects, features, and advantages of the presentinvention will be better understood from the following detaileddescription taken in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWING

FIG. 1 shows a top view of a gate array in block form.

FIG. 2 shows a schematic of a pair of gate array core cells.

FIG. 3 shows a schematic cross-sectional plan view of two adjacent gatearray core cells before metallization.

FIG. 4 is a schematic diagram of a merged SRAM and two ROM memory cells.

FIG. 5 shows the gate array core cells of FIG. 3 including a first andsecond layer of metal to provide a macro cell of the merged SRAM and ROMcells.

DETAILED DESCRIPTION OF THE INVENTION

A gate array integrated circuit which may be customized to performspecified system functions is shown in FIG. 1. The gate array typicallyincludes a plurality of input/output gates 11 around the periphery of achip 12 and which are coupled between one of a plurality of input/outputpads 13 and a plurality of core cells 14. The core cells 14 aretypically arranged on an internal portion of the chip 12 in an array ofrows and columns and comprise standard functions including combinatorialand sequential logic and other special functions including memory.

Referring to FIG. 2, two core cells 26 and 27 of the plurality of corecells 14 are shown schematically. The core cells 26 and 27 are shown asthey are manufactured on chip before metallization for interconnectionof the transistors and intraconnection of the core cells. The core cell26 includes two P-channel field effect transistors 15 and 16 havingtheir source-drain current paths connected in series, and two N-channelfield effect transistors 17 and 18 having their source-drain currentpaths connected in series. The core cell 27 is identical to the corecell 26 and includes field effect transistors 19, 21, 22, and 23. Thefield effect transistors 15, 16, 17, 18, 19, 21, 22, and 23 do not havetheir gates connected to another element. The core cells 26 and 27 arewell known in the art and are further described in T. Wong et al, "AHigh Performance 129K Gate CMOS Array," IEEE 1986 Custom IntegratedCircuits Conference, pp. 568-569.

In FIG. 3, a schematic cross-sectional plan of the core cells 26 and 27is illustrated at the level before contacts and metallization are added.Structures of FIG. 3 which are shown in FIG.2 are identified by thenumbers in FIG. 2. N-wells 24 and 25 are diffused into a P-typesubstrate 28 followed by the deposition of the gates of the field effecttransistors 15, 16, 17, 18, 19, 21, 22, and 23, and the diffusion ofactive areas 10 in a manner well known to those skilled in the art. Thefield effect transistors of the core cells 26 and 27 are arranged in amanner which allows the transistors to be coupled together by themetallization patterns and contacts into many different circuitconfigurations. When the transistors are interconnected to form a logicfunction, they are said to be personalized. The different metal andcontact patterns used to define the interconnections are known as themacro cells.

The macro cell library is a collection of macro cells which define awide variety of functions. A macro cell may require only one core cellas in a two input Nand gate, or it may require many core cells as in a4-bit adder. A major goal of the designer of a macro cell library is toobtain a high efficiency ratio which is a measure of how manytransistors in each core cell are actually used (interconnected andproviding functionality) in the personalization. For example, the twoinput Nand gate requires four transistors and, therefor, one core cellcan be used resulting in an efficiency of 100 percent. But a three inputNand gate requires 6 transistors provided by two core cells having 8transistors available and resulting in an efficiency of 6/8 or 75percent.

As gate arrays have increased in size, there has been more demand fornew functions including memory. When more functions are available, thefunctionality of a gate array may be increased and thus fewer chips arerequired in a system resulting in more competitive products. Providingmemory options on a gate array in the past have included dedicatedmemory arrays in addition to the core cell array and offering memorycells in the macro cell library. A significant draw back to the macrocell approach has been the inefficiency associated with the SRAM. ThisSRAM macro cell requires six transistors and so has an efficiency of 75percent. When providing significant amounts of memory this results in alarge percentage of the gate array being unusable.

A solution to this inefficiency is illustrated in FIG. 4 where a SRAMcell 29 is shown combined with a ROM function 31. The combination memorycell requires eight transistors and can be implemented in two core cellsresulting in an efficiency of 100 percent. Again, structures of FIG. 4which are shown in FIG. 3 are identified by the numbers in FIG. 3. Thesix transistor SRAM cell 29 comprises two inverters 32 and 33, and twopass transistors comprised of the field effect transistors 17 and 23.The field effect transistors 15 and 16 have their sources connected tothe supply voltage bus 1, their drains connected to nodes 37 and 38,respectively, and their gates connected to the nodes 38 and 37,respectively. The field effect transistors 18 and 22 have their sourcesconnected to the supply voltage bus 2, their drains connected to thenodes 37 and 38, respectively, and their gates connected to the nodes 38and 37, respectively. The field effect transistor 17 has a sourceconnected to the node 37, a gate connected to a SRAM word line 36, and adrain connected to a SRAM bit line 34. The field effect transistor 23has a source connected to the node 38, a gate connected to the SRAM wordline 36, and a drain connected to a SRAM bit line 35.

The six transistor SRAM configuration as depicted by the SRAM 29 iswidely known and used in the industry and works well in the gate arraycore cell implementation wherein all transistors have the same channellengths and channel widths. In operation, a single data bit is stored inthe cell by bringing the SRAM word line 36 high and forcing the SRAM bitline 35 low or high depending on the state of the data bit being stored.The SRAM word line is then brought low and the inverters 32 and 33 willlatch and store the written data bit. Upon reading the data bit from theSRAM cell 29, the SRAM word line 36 is brought high allowing the storeddata bit to control the level of the SRAM bit lines 34 and 35 throughthe pass transistors 17 and 23, respectively. By the action of the twoinverters 32 and 33, and depending on the state of the stored data bit,one of the SRAM bit lines 34 and 35 will go high and the other will golow.

The ROM function 31 comprises the field effect transistors 19 and 21therein providing the storage of two data bits. The field effecttransistor 19 has a source connected to the supply voltage bus 1, a gateconnected to the ROM word line 41, and a drain connected to the ROM bitline 39. The field effect transistor 21 has a source connected to thesupply voltage bus 1, a gate connected to the ROM word line 42, and adrain connected to the ROM bit line 43. The connection of the sources ofthe field effect transistors 19 and 21 to the supply voltage bus 1 isprogrammable. If a logical 1 is to be stored in a ROM location, then thesource is connected to the supply voltage bus 1 as previously described.For example, if the ROM word line 41 is brought low, the field effecttransistor 19 is selected and will conduct to bring the ROM bit line 39high. If a logical zero were to be stored in the ROM location, thesource is left floating or unconnected. For example, if the ROM wordline 41 is again brought low, the field effect transistor 19 is selectedbut will not connect the word line 39 to the supply voltage bus 1. Apulldown device in the ROM decoders will ensure the ROM bit line 39 ispulled down to a logical 0.

An advantage of the merged SRAM 29 and ROM function 31 as shown in FIG.4 is the ability to decode the SRAM bit separately from either of theROM bits. This is possible due to each memory bit having its own bit andword lines. The result is the capability of having two independentmemories (SRAM and ROM) on a gate array in the same area previouslyrequired for providing only the SRAM. FIG. 5 shows a possible macro cellimplementation of the merged SRAM 29 and ROM function 31 shown in FIG.4. The macro cell shown in FIG. 5 comprises 4 personalization layersincluding contact, first metal, via, and second metal.

By now it should be appreciated that there has been provided a gatearray macro cell having improved efficiency wherein a single SRAM bit iscombined with two ROM bits to utilize all prediffused transistors in thecore cell.

I claim:
 1. A semicustom integrated circuit having a plurality of corecells, each of said plurality of core cells having a plurality oftransistors, said semicustom integrated circuit comprising:first meansfor interconnecting a first portion of the plurality of transistors ofone of the plurality of core cells in a predetermined manner forproviding a first type of memory cell; and second means forinterconnecting the remaining portion of the plurality of transistors ofsaid one of the plurality of core cells in a predetermined manner forproviding at least one second type of memory cell.
 2. The semicustomintegrated circuit according to claim 1 wherein said first means furthercomprises a plurality of metallization patterns coupled to said firstportion of the plurality of transistors for providing said first type ofmemory cell.
 3. The semicustom integrated circuit according to claim 2wherein said second means further comprises a plurality of metallizationpatterns coupled to said remaining portion of the plurality oftransistors for providing said at least one second type of memory cell.4. The semicustom integrated circuit according to claim 3 wherein saidfirst type of memory cell and said at least one second type of memorycell may each be accessed individually.
 5. The semicustom integratedcircuit according to claim 4 wherein said plurality of transistorscomprises CMOS transistors.
 6. A gate array core cell comprising:a firstsupply voltage bus for receiving a first supply voltage; a second supplyvoltage bus for receiving a second supply voltage; a first bit line; asecond bit line a third bit line; a fourth bit line; a first word line;a second word line; a third word line; a first field effect transistorhaving a drain coupled to said first bit line, a gate coupled to saidfirst word line, and having a source; a second field effect transistorhaving a drain coupled to said second bit line, a gate coupled to saidfirst word line, and having a source; a third field effect transistorhaving a source coupled to said first supply voltage bus, a gate coupledto the source of said second field effect transistor, and a draincoupled to said source of said first field effect transistor; a fourthfield effect transistor having a source coupled to said second supplyvoltage bus, a gate coupled to the source of said second field effecttransistor, and a drain coupled to the source of said first field effecttransistor; a fifth field effect transistor having a source coupled tosaid first supply voltage bus, a gate coupled to the source of saidfirst field effect transistor, and a drain coupled to the source of saidsecond field effect transistor; a sixth field effect transistor having asource coupled to said second supply voltage bus, a gate coupled to thesource of said first field effect transistor, and a drain coupled to thesource of said second field effect transistor; a seventh field effecttransistor having a source selectively coupled to said first supplyvoltage bus, a gate coupled to said second word line, and a draincoupled to said third bit line; and an eighth field effect transistorhaving a source selectively coupled to said first supply voltage, a gatecoupled to said third word line, and a drain coupled to said fourth bitline.
 7. A semicustom integrated circuit including a plurality of corecells, each of said plurality of core cells having a plurality oftransistors, one of the plurality of core cells comprising:a first typeof memory cell utilizing a first portion of the plurality of transistorsof one of the plurality of core cells coupled in a predetermined mannerfor providing data storage and retrieval operations, said first type ofmemory cell utilizing less than the available number of the plurality oftransistors of one of the plurality of core cells; and at least onesecond type of memory cell utilizing a second portion of the pluralityof transistors of one of the plurality of core cells coupled in apredetermined manner for providing data retrieval operations, said firstand second types of memory cells substantially utilizing the pluralityof transistors of one of the plurality of core cells.
 8. The semicustomintegrated circuit according to claim 7 wherein said at least one secondmemory cell includes a first transistor having a gate, a source and adrain, said gate being coupled for receiving a first word line signal,said drain being coupled for receiving a first bit line signal.
 9. Thesemicustom integrated circuit according to claim 8 wherein said sourceof said first transistor is coupled to a first power supply conductor.10. The semicustom integrated circuit according to claim 8 wherein saidsource of said first transistor is open-circuited.
 11. The semicustomintegrated circuit according to claim 8 wherein said first type ofmemory cell includes:a second transistor having a gate, a source and adrain, said gate being coupled for receiving a second word line signal,said drain being coupled for receiving a second bit line signal; a thirdtransistor having a gate, a source and a drain, said source beingcoupled to a first power supply conductor, said drain being coupled tosaid source of said second transistor; a fourth transistor having agate, a source and a drain, said drain being coupled to said drain ofsaid third transistor, said source being coupled to a second powersupply conductor, said gate being coupled to said gate of said thirdtransistor; a fifth transistor having a gate, a source and a drain, saidsource being coupled to said power supply conductor; a sixth transistorhaving a gate, a source and a drain, said source being coupled to saidsecond power supply conductor, said drains of said fifth and sixthtransistors being coupled together to said gates of said third andfourth transistors, said gates of said fifth and sixth transistors beingcoupled to said source of said second transistor; and a seventhtransistor having a gate, a source and a drain, said source beingcoupled to said drains of said fifth and sixth transistors, said gatebeing coupled for receiving said second word line signal, said drainbeing coupled for receiving a third bit line signal.
 12. A method ofcombining a first type of memory cell and at least one second type ofmemory cell on a semicustom integrated circuit including a plurality ofcore cells, each of said plurality of core cells having a plurality oftransistors, comprising the steps of:allocating a first portion of theplurality of transistors of one of the plurality of core cells andinterconnecting said first portion of the plurality of transistors in apredetermined manner via a first plurality of metallization patterns forproviding data storage and retrieval operations of the first type ofmemory cell, said first type of memory cell utilizing less than theavailable number of the plurality of transistors of one of the pluralityof core cells; and allocating a second portion of the plurality oftransistors of one of the plurality of core cells and interconnectingsaid second portion of the plurality of transistors in a predeterminedmanner via a second plurality of metallization patterns for providingdata retrieval operations of the at least one second type of memorycell, said first and second types of memory cells substantiallyutilizing the plurality of transistors of one of the plurality of corecells.